VLSI: Techniques for Efficient Standard Cell Placement

In the physical designing of the chip, placement is one of the most important steps in the design flow, this paper gives the basic overview of the placement algorithms being used with shrinking technology node for the automatic placement of cells which gives an optimized design in terms of chip area, speed and cost. Basically the emphasis will be on recent trends of Wire-length driven placement (higher technology node) which includes the different ways to estimate wire length and also the Timing driven placement technique (lower technology node) i.e. by meeting the setup and hold time requirements (STA) of the design and thus bringing out the advancement and challenges in placement research techniques being used. Thereby concluding an efficient way of arranging the logic cells on VLSI chip.